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C3U3EN FPGA FX3 Development Kit

SKU: c3u3en

Availability: In stock

$545.00
USB3.0-ALTERA-DDR2 board is a FPGA + USB3.0 FX3 Development Board well-designed by Beijing Huanor-Mingke Electronic Tech Center . The main chip architecture: CYUSB3014(FX3 USB3.0)+ EP3C40F484 (FPGA)+ MT47H64M16HR(1Gb DDR2, 2pcs).

Details

    USB3.0-ALTERA-DDR2 board is a FPGA + USB3.0 FX3 Development Board well-designed by Beijing Huanor-Mingke Electronic Tech Center (http://www.huanor.com). The main chip architecture: CYUSB3014(FX3 USB3.0)+ EP3C40F484 (FPGA)+ MT47H64M16HR(1Gb DDR2, 2pcs).
    USB3.0 chip uses the Cypress FX3 series CYUSB3014-BZXI. Cypress EZ-USB FX3 is the next generation USB 3.0 peripheral controller providing highly integrated and flexible features that enable developers to add USB 3.0 functionality to any system. EZ-USB FX3 is fully compliant to USB 3.0 v1.0 specification and is also backward compatible with USB 2.0. It is also complaint with the Battery Charging Specification v1.1 and USB 2.0 OTG Specification v2.0. EZ-USB FX3 contains 512 KB of on-chip SRAM for code and data. EZ-USB FX3 also provides interfaces to connect to serial peripherals such as UART, SPI, I2C, and I2S.
    Usb3.0-Altera-DDR2 board with 8 layers of circuit is designed according to industry standard and two DDR2 chips can work stably in 200MHz (FPGAs -6 rating). The transmission lines between the FPGA and USB3.0 chip and, external IOs are of equal length, which ensure that the signal transmission is of high speed and reliable. Two DDR2 chips with 1Gbits use a separate address bus and data bus, support the data transfer mode of ping-pong turns.
    Usb3.0-Altera-DDR2 board is developed based on the Cypress SDK and an increase of an FPGA chip make it closer to the actual applications. The example provided by us is optimized on the basis of the Cypress SDK and the data transfer speed is up to 310MBytes/s (No data error, no data loss, the average transfer speed). Product Features - FPGA USB3.0 FX3 Development Kit
● FPGA: EP3C40F484C8N.
● SuperSpeed USB Controller: CYUSB3014-BZXI.
● High-speed and stable data transmission example (source code provided), the data transfer speed is up to 310MBytes/s (No data error, no data loss, the average transfer speed).
● Two DDR2 chips with 1Gbits use a separate address bus and data bus, support the data transfer mode of ping-pong turns. The DDR2 can work stably in 200MHz (FPGAs -6 rating).
● FIFO based on DDR2 SDRAM(FPGA source code), to meet the needs of a large cache. It is an ideal choice for data acquisition. DDR2 controller does not use a NIOS II system, so that the data transmission more efficient.
● The transmission lines between the FPGA and Expansion header IOs are of equal length, which ensure that users can connect an external high-speed devices directly through the development board, to quickly complete the product design.
● Data transfer between the FPGA with CYUSB3014 dual-channel, high-speed data transmission channel and low-speed control instruction transmission channel is independent.
● Rich software features support, so you can be faster and more efficient learning and development.

Hardware Features - FPGA USB3.0 FX3 Development Kit
● USB3.0 Device: Cypress EZ-USB FX3 CYUSB3014-BZXI.
● FPGA Device: Cyclone III EP3C40F484C8N.
● Memory Devices: 1Gb DDR2 MT47H64M16HR, 2pcs. 64Mb FLASH M25P64, 2pcs. 256Kb I2C EEPROM 24LC256.
● Power Device: Multi-Channel Power Management IC TPS650243RHBR.
● RS232 Device: True RS-232 Transceivers MAX3232E.
● Clocking: 50-MHz onboard oscillator.
● Switches and indicators: 4 push buttons and 4 LEDs.
● Power supply: USB3.0 Type Micro-B port (5 V). DC Power Jack (5V).
● Extension connectors: 72 signals(24 1.8V, 32 3.3V, 16 2.5V/3.3V configurable).

Software Features - FPGA USB3.0 FX3 Development Kit
● FPGA-> USB-> PC and PC-> USB-> FPGA data transfer example.
● USB3.0 read data transfer speed test example.
● USB3.0 write data transfer speed test example.
● 16-channel virtual logic analyzer example.
● 4-channel virtual oscilloscope example.
● 3 KEYs and 3 LEDs control example.
● Including cypress SDK firmware examples, as follows.
firmware
├─basic_examples
│  ├─cyfxbulklpautoenum
│  ├─cyfxbulklpauto_cpp
│  ├─cyfxbulklpotg
│  ├─cyfxbulksrcsink
│  ├─cyfxbulkstreams
│  ├─cyfxflashprog
│  ├─cyfxisolpauto
│  ├─cyfxisolpmaninout
│  ├─cyfxisosrcsink
│  ├─cyfxusbdebug
│  ├─cyfxusbhost
│  └─cyfxusbotg
├─dma_examples
│  ├─cyfxbulklpauto
│  ├─cyfxbulklpautomanytoone
│  ├─cyfxbulklpautoonetomany
│  ├─cyfxbulklpautosig
│  ├─cyfxbulklplowlevel
│  ├─cyfxbulklpmandcache
│  ├─cyfxbulklpmaninout
│  ├─cyfxbulklpmanmanytoone
│  ├─cyfxbulklpmanonetomany
│  ├─cyfxbulklpmanual
│  ├─cyfxbulklpmanual_rvds
│  ├─cyfxbulklpman_addition
│  ├─cyfxbulklpman_removal
│  └─cyfxbulklpmulticast
├─huanor_examples
│  └─HuanorFx3Example
├─serialif_examples
│  ├─cyfxgpioapp
│  ├─cyfxgpiocomplexapp
│  ├─cyfxuartlpdmamode
│  ├─cyfxuartlpregmode
│  ├─cyfxusbi2cdmamode
│  ├─cyfxusbi2cregmode
│  ├─cyfxusbi2sdmamode
│  ├─cyfxusbspidmamode
│  ├─cyfxusbspigpiomode
│  └─cyfxusbspiregmode
├─slavefifo_examples
│  ├─slfifoasync
│  └─slfifosync
└─uvc_examples
   ├─cyfxuvcinmem
   └─cyfxuvcinmem_bulk
● Including cypress SDK application examples, as follows.
application
├─cpp
│  ├─bulkloop
│  ├─Fx3Client
│  └─streamer
└─c_sharp
   ├─bulkloop
   ├─controlcenter
   └─streamer

Resources - FPGA USB3.0 FX3 Development Kit
● Cypress EZ-USB FX3 SDK 1.2:
FX3_SDK,CySuiteUSB3_x64,CySuiteUSB3_x86,Eclipse,ARM_GCC.
● Cypress USB3.0 training documentation.
● Cypress EZ-USB FX3 Development board schematics and PCB files (including gerber file).
● Usb3.0-Altera-DDR2 development board schematics and pcb file (pdf format).
● Usb3.0-Altera-DDR2 development board all the program source code(PC Application, Firmware, FPGA).
● Usb3.0-Altera-DDR2 development board user manual and other manuals.

Product List - FPGA USB3.0 FX3 Development Kit
1,  Usb3.0-Altera-DDR2 board. ------x1
2,  USB3.0 Cable. ------x1
3,  serial Cable. ------x1
4,  USB Blaster Download Cable (Includes the adapter board). ------x1
5,  Product CD.------x1

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